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INTEGRATED CIRCUITS
74ALVCH16821 20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)
Product specification IC24 Data Handbook 1998 May 29
Philips Semiconductors
Philips Semiconductors
Product specification
20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)
74ALVCH16821
FEATURES
* Wide supply voltage range of 1.2V to 3.6V * Complies with JEDEC standard no. 8-1A * Current drive 24 mA at 3.0 V * CMOS low power consumption * Direct interface with TTL levels * MULTIBYTETM flow-through standard pin-out architecture * Low inductance multiple VCC and ground pins for minimum noise
and ground bounce
DESCRIPTION
The 74ALVCH16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-State output buffer. The two sections of each register are controlled independently by the clock (nCP) and Output Enable (nOE) control gates. Each register is fully edge triggered. The state of each D input, one set-up time before the Low-to-High clock transition, is transferred to the corresponding flip-flop's Q output. When nOE is LOW, the data in the register appears at the outputs. When nOE is HIGH, the outputs are in high impedance OFF state. Operation of the nOE input does not affect the state of the flip-flops. The 74ALVCH16821 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors.
* All data inputs have bus hold * Output drive capability 50 transmission lines @ 85C
QUICK REFERENCE DATA
SYMBOL tPHL/tPLH CI CPD Fmax GND = 0V; Tamb = 25C; tr = tf 2.5ns PARAMETER Propagation delay nCP to nQn Input capacitance Power dissipation capacitance per buffer Maximum clock frequency
CONDITIONS VCC = 2.5V, CL = 30pF VCC = 3.3V, CL = 50pF Outputs enabled Outputs disabled
TYPICAL 2.6 2.5 5.0 33 17 250 350
UNIT ns pF pF MHz
VI = GND to VCC1 VCC = 2.5V, CL = 30pF VCC = 3.3V, CL = 50pF
NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD x VCC2 x fi + S (CL x VCC2 x fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; S (CL x VCC2 x fo) = sum of outputs.
ORDERING INFORMATION
PACKAGES 56-Pin Plastic SSOP Type III 56-Pin Plastic TSSOP Type II TEMPERATURE RANGE -40C to +85C -40C to +85C OUTSIDE NORTH AMERICA 74ALVCH16821 DL 74ALVCH16821 DGG NORTH AMERICA ACH16821 DL ACH16821 DGG DWG NUMBER SOT371-1 SOT364-1
1998 May 29
2
853-2066 19467
Philips Semiconductors
Product specification
20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)
74ALVCH16821
PIN DESCRIPTION
PIN NUMBER 55, 54, 52, 51, 49, 48, 47, 45, 44, 43 42, 41, 40, 38, 37, 36, 34, 33, 31, 30 2, 3, 5, 6, 8, 9, 10, 12, 13, 14 15, 16, 17, 19, 20, 21, 23, 24, 26, 27 1, 28 56, 29 4, 11, 18, 25, 32, 39, 46, 53 7, 22, 35, 50 SYMBOL 1D0 - 1D9 Data in uts inputs 2D0 - 2D9 1Q0 - 1Q9 Data outputs out uts 2Q0 - 2Q9 1OE, 2OE 1CP, 2CP GND VCC Output enable inputs (active-Low) Clock pulse inputs (active rising edge) Ground (0V) Positive supply voltage FUNCTION
FUNCTION TABLE
INPUTS nOE L L L H L X Z } = = = = = = CP } Dx L H X OUTPUT Q L H Q0 Z
H X X HIGH voltage level LOW voltage level Don't care High impedance OFF state LOW to HIGH clock transition Not a LOW-to-HIGH clock transition
LOGIC SYMBOL
1 56
1OE
1CP 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D9 55 54 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31 30
PIN CONFIGURATION
1OE 1Q0 1Q1 GND 1Q2 1Q3 VCC 1Q4 1Q5 1Q6 GND 1Q7 1Q8 1Q9 2Q0 2Q1 2Q2 GND 2Q3 2Q4 2Q5 VCC 2Q6 2Q7 GND 2Q8 2Q9 2OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1CP 1D0 1D1 GND 1D2 1D3 VCC 1D4 1D5 1D6 GND 1D7 1D8 1D9 2D0 2D1
2 3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 2D2 GND 2D3 2D4 2D5 VCC 2D6 2D7 GND 2D8 2D9 2CP 23 24 26 27
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9 2OE 2CP
28
29
SH00127
SH00001
1998 May 29
3
Philips Semiconductors
Product specification
20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)
74ALVCH16821
LOGIC SYMBOL (IEEE/IEC)
1OE 1CP 2OE 2CP 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D9 1 56 28 29 55 54 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31 30 3D 4 EN2 C1 EN4 C3 1D 2 2 3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26 27 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9
SH00003
LOGIC DIAGRAM
nD0 nD1 nD2 nD3 nD4 nD5 nD6 nD7 nD8 nD9
D
D
D
D
D
D
D
D
D
D
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
nCP
nOE nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 nQ8 nQ9
SH00004
1998 May 29
4
Philips Semiconductors
Product specification
20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)
74ALVCH16821
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL PARAMETER DC supply voltage 2.5V range (for max. speed performance @ 30 pF output load) VCC DC supply voltage 3.3V range (for max. speed performance @ 50 pF output load) DC Input voltage range DC output voltage range Operating free-air temperature range Input rise and fall times VCC = 2.3 to 3.0V VCC = 3.0 to 3.6V CONDITIONS MIN 2.3 3.0 0 0 -40 0 0 MAX 2.7 V 3.6 VCC VCC +85 20 10 V V C ns/V UNIT
VI VO Tamb tr, tf
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL VCC IIK VI IOK VO IO IGND, ICC Tstg PTOT PARAMETER DC supply voltage DC input diode current DC in ut voltage input DC output diode current DC output voltage DC output source or sink current DC VCC or GND current Storage temperature range Power dissipation per package -plastic medium-shrink (SSOP) -plastic thin-medium-shrink (TSSOP) For temperature range: -40 to +125 C above +55C derate linearly with 11.3 mW/K above +55C derate linearly with 8 mW/K VI t0 For control pins1 For data inputs1 VO uVCC or VO t 0 Note 1 VO = 0 to VCC CONDITIONS RATING -0.5 to +4.6 -50 -0.5 to +4.6 -0.5 to VCC +0.5 "50 -0.5 to VCC +0.5 "50 "100 -65 to +150 850 600 V mA V mA mA C mW UNIT V mA
NOTE: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 May 29
5
Philips Semiconductors
Product specification
20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)
74ALVCH16821
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40C to +85C MIN VIH HIGH level Input voltage VCC = 2.3 to 2.7V VCC = 2.7 to 3.6V LOW level Input voltage VCC = 2.3 to 2.7V VCC = 2.7 to 3.6V VCC = 2 3 to 3 6V; VI = VIH or VIL; IO = -100A 100A 2.3 3.6V; VCC = 2.3V; VI = VIH or VIL; IO = -6mA VO OH HIGH level output voltage VCC = 2.3V; VI = VIH or VIL; IO = -12mA VCC = 2.7V; VI = VIH or VIL; IO = -12mA VCC = 3.0V; VI = VIH or VIL; IO = -12mA VCC = 3.0V; VI = VIH or VIL; IO = -24mA VCC = 2 3 to 3 6V; VI = VIH or VIL; IO = 100A 2.3 3.6V; VCC = 2.3V; VI = VIH or VIL; IO = 6mA VOL LOW level output voltage VCC = 2.3V; VI = VIH or VIL; IO = 12mA VCC = 2.7V; VI = VIH or VIL; IO = 12mA VCC = 3.0V; VI = VIH or VIL; IO = 24mA II IOZ ICC ICC IBHL Input leakage current g 3-State output OFF-state current Quiescent supply current Additional quiescent supply current Bus hold LOW sustaining current VCC = 2 3 to 3 6V; 2.3 3.6V; VI = VCC or GND VCC = 2.7 to 3.6V; VI = VIH or VIL; VO = VCC or GND VCC = 2.3 to 3.6V; VI = VCC or GND; IO = 0 VCC = 2.3V to 3.6V; VI = VCC - 0.6V; IO = 0 VCC = 2.3V; VI = 0.7V2 VCC = 3.0V; VI = Bus hold HIGH sustaining current Bus hold LOW overdrive current Bus hold HIGH overdrive current 0.8V2 45 75 -45 -75 500 -500 -175 VCC*0.2 02 VCC*0.3 VCC*0.6 VCC*0.5 VCC*0.6 VCC*1.0 1.7 2.0 TYP1 1.2 V 1.5 1.2 1.5 VCC VCC*0.08 VCC*0.26 VCC*0.14 VCC*0.09 VCC*0.28 GND 0.07 0.15 0.14 0.27 0.1 0.1 0.2 150 - 150 0.20 0 20 0.40 0.70 0.40 0.55 5 10 40 750 A A A A A V V V V 0.7 V 0.8 MAX UNIT
VIL
IBHH IBHLO IBHHO
VCC = 2.3V; VI = 1.7V2 VCC = 3.0V; VI = VCC = 3.6V2 VCC = 3.6V2 2.0V2
A A A
NOTES: 1. All typical values are at Tamb = 25C. 2. Valid for data inputs of bus hold parts.
1998 May 29
6
Philips Semiconductors
Product specification
20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)
74ALVCH16821
AC CHARACTERISTICS FOR VCC = 2.3V TO 2.7V RANGE
GND = 0V; tr = tf 2.0ns; CL = 30pF SYMBOL LIMITS PARAMETER Propagation delay nCP to nQn 3-State output enable time nOEn to nQn 3-State output disable time nOEn to nQn nCP pulse width HIGH or LOW Set up time nDn to nCP Hold time nDn to nCP Maximum clock pulse frequency WAVEFORM MIN tPLH/tPHL tPZH/tPZL tPHZ/tPLZ tW tSU th Fmax 1, 4 2, 4 2, 4 3, 4 3, 4 3, 4 1, 4 1.0 1.0 1.0 3.0 1.4 0.4 150 VCC = 2.5V 0.2V TYP1 2.6 2.8 2.2 1.8 0.3 0.0 250 MAX 5.8 6.6 5.7 ns ns ns ns ns ns MHz UNIT
NOTE: 1. All typical values are at VCC = 2.5V and Tamb = 25C.
AC CHARACTERISTICS FOR VCC = 3.0V TO 3.6V RANGE AND VCC = 2.7V
GND = 0V; tr = tf 2.5ns; CL = 50pF SYMBOL LIMITS PARAMETER Propagation delay nCP to nQn 3-State output enable time nOEn to nQn 3-State output disable time nOEn to nQn nCP pulse width HIGH or LOW Set up time nDn to nCP Hold time nDn to nCP Maximum clock pulse frequency WAVEFORM MIN tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tW tSU th Fmax 1, 4 2, 4 2, 4 3, 4 3, 4 3, 4 1, 4 1.0 1.0 1.0 3.3 1.0 0.8 150 VCC = 3.3 0.3V TYP1 2.5 2.3 2.8 0.2 0.2 0.4 350 MAX 4.5 5.1 4.6 MIN 1.0 1.0 1.0 3.3 1.2 0.6 150 VCC = 2.7V TYP1 2.8 3.2 3.1 1.7 0.3 -0.3 300 MAX 5.3 6.2 5.0 ns ns ns ns ns ns MHz UNIT
NOTES: 1. All typical values are at Tamb = 25C.
1998 May 29
7
Philips Semiconductors
Product specification
20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)
74ALVCH16821
AC WAVEFORMS
VCC = 2.3 TO 2.7 V RANGE 1. VM = 0.5 V 2. VX = VOL + 0.15V 3. VY = VOH - 0.15V 4. VI = VCC 5. VOL and VOH are the typical output voltage drop that occur with the output load. VCC = 3.0 TO 3.6 V RANGE AND VCC = 2.7 V 1. VM = 1.5 V 2. VX = VOL + 0.3V 3. VY = VOH - 0.3V 4. VI = 2.7 V 5. VOL and VOH are the typical output voltage drop that occur with the output load.
VI nCP INPUT GND VI nDn INPUT GND VOH nQn OUTPUT VOL VM VM VM tsu th tsu th
SH00129
Waveform 3. Set up and hold times.
1/fMAX VI nCP INPUT GND VOH nQn OUTPUT VOL VM VM VM tw tPHL tPLH
TEST CIRCUIT
VCC S1 2 * VCC Open GND
VI PULSE GENERATOR D.U.T. RT
VO
RL = 500
SH00128
CL
RL = 500
Waveform 1.
The input (nCP) to output propagation delays. Test Circuit for switching times
VI nOE INPUT GND VM
DEFINITIONS
RL = Load resistor CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators.
SWITCH POSITION
tPLZ tPZL TEST tPLH/tPHL VM VX tPLZ/tPZL tPHZ/tPZH S1 Open 2 < VCC
GND
VCC < 2.7V 2.7-3.6V
VI VCC 2.7V
VCC OUTPUT LOW-to-OFF OFF-to-LOW VOL
SV00906
tPHZ VOH OUTPUT HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled VY VM tPZH
Waveform 4. Load circuitry for switching times
SW00308
Waveform 2. The 3-State enable and disable times.
1998 May 29
8
Philips Semiconductors
Product specification
20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)
74ALVCH16821
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm
SOT371-1
1998 May 29
9
Philips Semiconductors
Product specification
20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)
74ALVCH16821
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm
SOT364-1
1998 May 29
10
Philips Semiconductors
Product specification
20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)
74ALVCH16821
NOTES
1998 May 29
11
Philips Semiconductors
Product specification
20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)
74ALVCH16821
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-04553
Philips Semiconductors
1998 May 29 12

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